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HiSilicon K3V1 Hi3611 (K3)

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Generel Characteristics: 
DesignerCompany which designed the semiconductor component HiSilicon
Type K3V1 Hi3611
Codename K3
Year Released 2009
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) ARMv5TEJ
Type of processor core(s)Type and allocation of processor core(s) ARM926EJ-S
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   SDRAM, LPDDR SDRAM
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 16 bit
Number of data bus channels 1 ch


Clock FrequenciesClock Frequencies: 
Recommended Minimum Clock Frequency 360 MHz min.
Recommended Maximum Clock Frequency 460 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 16 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 16 Kbyte D-Cache

Technology and Packaging: 
Feature SizeThe minimum physical dimension in the integrated circuit which can be fabricated with the given semiconductor technology 130 nm
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor

Additional Features: 
Special Features Graphics Engine, 200KB shared SRAM, RawNAND / NOR..

Datasheet Attributes: 
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Preliminary
AddedThe exact time of the datasheet addition 2010-06-11 09:32
 
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