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Philips PR31700 (Poseidon v1.5)

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Generel Characteristics: 
DesignerCompany which designed the semiconductor component Philips
Type PR31700
Codename Poseidon v1.5
Year Released 1998
FunctionMain function of the component  Application Processor

ArchitectureArchitecture: 
Width of Machine WordMaximum bitwidth of ALU operands. Width of machine word can also be defined in different ways (register width, instruction width, etc.) in case of recent microprocessors. 32 bit
Supported Instruction Set(s) MIPS I, MIPS II
Type of processor core(s)Type and allocation of processor core(s) MIPS R3000
Number of processor core(s) single-core

BusesBuses: 
Memory Interface(s):   Yes
Data Bus WidthMaximum selectable bit width of primary data bus (RAM) of memory interface 32 bit
Number of data bus channels 1 ch


Clock FrequenciesClock Frequencies: 
Recommended Maximum Clock Frequency 75 MHz max.

Cache MemoriesCache Memories: 
L1 Instruction Cache per CoreCapacity of level 1 instruction cache per processor core 4 Kbyte I-Cache
L1 Data Cache per CoreCapacity of level 1 data cache per processor core 1 Kbyte D-Cache

Technology and Packaging: 
Semiconductor Technology:   CMOSComplementary Metal-oxide - Semiconductor Field Effect Transistor
Number of Transistors Integrated 110000

Additional Features: 
Special Features MMU, multi-channel DMA controller..

Datasheet Attributes: 
Data IntegrityData integrity level determines the integrity of the published information. Final datasheets are not intended to be modified in the future, preliminary ones can be based on unofficial information or speculations, incomplete ones are also preliminary b  Final
AddedThe exact time of the datasheet addition 2006-01-01 06:00
 
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